(1) Field of the Invention
The present invention relates to a process used to fabricate a cell for a dynamic random access memory, (DRAM), device, and more specifically to a fabrication process in which the area of the DRAM cell can be reduced using self-alignment processes for bit line contact and capacitor node structures.
(2) Description of the Prior Art
In order to satisfy demands for high density DRAM semiconductor chips, micro-miniaturization, or the use of sub-micron features, used for DRAM designs, are employed. The attainment of micro-miniaturazation, or sub-micron features, has been mainly accomplished by advances in specific semiconductor fabrication disciplines, as photolithography and dry etching. The use of more sophisticated exposure cameras, as well as the use of more sensitive photoresist materials, have allowed sub-micron images to be created in photoresist layers. In addition the development of more advanced dry etching tools and etch recipes, have allowed the sub-micron images in overlying photoresist layers to be successfully transferred to underlying materials, used in the creation of advanced semiconductor devices.
However to achieve DRAM cell densities of 1 gigabit, or greater, new design, in addition to process enhancements, may be needed. Currently the area needed for a DRAM cell is equal to between about eight to 12 times the minimum feature used, sometimes referred to as 8F.sup.2 or 12F.sup.2. However the decreasing feature dimensions, used with an 8F.sup.2 technology, place stringent limitations on specific photolithographic alignment steps. For example any mis-alignment, occurring with the opening of the bit line contact hole, or the storage node hole, can result in unwanted leakages or shorts, when designing to a 8F.sup.2 technology.
This invention will describe a fabrication process for a DRAM cell, capable of densities of 1 gigabit or greater, in which 8F.sup.2 technology is used, but featuring self-alignment procedures, specifically for the bit line, and storage node structures, thus minimizing the mis-alignment possibility that can occur when using non self-aligned counterparts. This invention will also feature the use of polysilicon plugs, when used in combination with the self-aligned procedures, enhance the 8F.sup.2 technology used for high density DRAM cells. Prior art such as Rosner, in U.S. Pat. No. 5,600,162, describe a DRAM cell layout, however that DRAM layout does not offer the self-alignment features, or does it offer the process used to create a high density DRAM cell, using the novel self-alignment processes.